1. Field of the Invention
The present invention generally relates to integrated circuits and, more particularly to input/output (I/O) architecture, and read/write systems for high bandwidth semiconductor memories.
2. Description of the Related Art
Increasing the speed of operation and bandwidth continue to be one of the incentives behind evolutionary changes in the design, development, and implementation of memory circuits. For example, for dynamic random access memories (DRAMs), the extended data output (EDO) architecture was developed to enhance memory bandwidth. With synchronous DRAMs (SDRAMs), the ability to channel the data as well as data pre-fetch schemes have helped increase the speed, throughput, and bandwidth of the memory. For example, the quad data rate (QDR) SRAM uses a four-bit pre-fetch technique to quadruple the bandwidth of the memory circuit. However, this increase in bandwidth is often accompanied by a significant increase in the overall size and cost of the memory device.
As mentioned, one of the drawbacks of conventional QDR SRAMs is the corresponding increase in the overall size, and specifically, the number of I/O interconnect lines required to process the quad bits during read and write operations. For example, in a QDR SRAM having a by N organization (or ×N, such as ×16 or ×32), a 4-bit pre-fetch results in 4N bits of data being output from the memory array in read mode. Usually, the total columns in an array are divided into two sets of even and odd columns, each delivering N bits of data. The 2N columns connect to corresponding 2N sense amplifiers, with the 2N sense amplifiers driving 2N global I/O lines. Thus, a 2:1 parallel to serial conversion at the output takes place prior to the data being applied to the N data output (DQ) registers. This process is reversed for the write mode of operation, wherein a serial-to-parallel conversion turns a serial bit into quad bits for QDR.
The ability to achieve the cycle time associated with SRAM technology by using a DRAM has not yet been achieved. Those skilled in the art acknowledge that one can achieve a 4× density improvement (bit density) using DRAM over SRAM. For example, a 16 Mb SRAM approximates to a 128 Mb DRAM. However, a DRAM is much slower than its SRAM counterpart. Thus, it would be very beneficial to utilize DRAM technology due to its increased memory capacity, but to increase the DRAM speed in order to compete with SRAM processing speed. Thus, the ability to achieve the cycle time associated with SRAM technology by using a DRAM is desirable.
Separate I/O QDR SRAMs are the preferred solution in the networking/communications SRAM-memory space. Separate I/O allows read and write buses to be loaded simultaneously as memory operations constantly swap between read and write cycles. FIG. 1 shows a conventional SRAM QDR timing diagram with an 8 ns cycle, and a burst of 4. Moreover, conventional DRAM banking solutions use any number of banks to improve cycle time and data rate by:
DRAM Cycle
# of Banks
For example, a 16 ns DRAM with two banks can provide an 8 ns cycle part. FIG. 2 illustrates a conventional two-bank DRAM QDR timing diagram with an 8 ns cycle, and a burst of 4. As shown, banking protocols exist which partition the memory array into several different arrays, which can then be independently addressable. That is, the partition of the memory array occurs in the bank. Conventionally, as illustrated in FIG. 1, in an 8 ns timing protocol, a first bank (Bank 1) is accessed. After an 8 ns cycle lapses, only then can the same bank (Bank 1) be accessed.
Thus, in a single bank solution as illustrated in FIGS. 1-2, the same bank may be accessed only every 8 ns (the length of the entire cycle time), and during the cycle, only other banks may be accessed, not the same bank. By utilizing a multi-bank approach, for example, four banks, bandwidth maximization is achieved; as such data throughput is maximized. However, the disadvantage of such multi-banking approaches is it breaks away from the desired randomness, which is sought in banking address operations. Therefore, there is a need to access the same bank back-to-back using a multi-bank approach.
The advantage of DRAM as a replacement of SRAM memory space is becoming very popular as merged logic/DRAM processes and novel circuit techniques have enabled DRAM cycle times to shrink considerably. The need for separate I/O SRAMs with a QDR protocol has emerged as one of the standards for communication applications. Thus, there remains a need for a DRAM-based solution for the Quad Data Rate timing protocol, which allows access to the same bank during back-to-back operations.